1. Field of the Invention
This invention relates to integrated circuits, and more particularly, to built-in mechanisms for testing integrated circuits.
2. Description of the Related Art
Circuitry to support scan testing may provide internal access to an integrated circuit (IC). Scan circuitry may be implemented by forming chains of scannable elements. Data may be serially shifted through the scannable elements of the scan chain. This may allow for the input of test stimulus data, as well as the capture and shifting out of test result data. Using available scan circuitry, manufacturing tests may be conducted on ICs prior to their shipment to a customer in order to verify the circuitry therein. Scan circuitry may also support hardware debugging during the development phase of an IC, providing information for future revisions thereof.
In order to perform a scan test, test stimulus data may be shifted into a scan chain. Once each bit has reached its target scan element, the test stimulus data may be applied to circuitry in the IC, and a clock signal may be pulsed. After the pulsing of the clock signal, test result data may be captured and shifted from the IC (e.g., into a test system) for further analysis. Multiple tests may be conducted for a given scan chain using different test vectors. Furthermore, many IC's include multiple scan chains. Each of the multiple scan chains in an IC may be separate an independent from one another. Thus, multiple tests may be conducted on each of the multiple scan chains in an IC.